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Glossary VHDL / Term

aggregate

  1. The kind of expression, denoting a value of a composite type. The value is specified by giving the value of each of the elements of the composite type. Either a positional association or a named association may be used to indicate which value is associated with which element.
  2. A kind of target of a variable assignment statement or signal assignment statement assigning a composite value. The target is then said to be in the form of an aggregate.

Permanent link aggregate - Creation date 2021-04-03


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