Glossaria.net

Glossary VHDL / Term

Analysis

The syntax checking and compilation of a VHDL design into a design library.


The syntactic and semantic analysis of source code in a VHDL design file and the insertion of intermediate form representations of design units into a design library.

Permanent link Analysis - Modification date 2021-09-14 - Creation date 2021-06-13


< allocator Glossary / VHDL anonymous >