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Glossary VHDL / Term

update

An action on the value of a signal, variable, or file. The value of a signal is said to be updated when the signal appears as the target (or a component of the target) of a signal assignment statement, (indirectly) when it is associated with an interface object of mode out, buffer, inout, or linkage, or when one of its subelements (individually or as part of a slice) is updated. The value of a signal is also said to be updated when it is subelement or slice of a resolved signal, and the resolved signal is updated. The value of a variable is said to be updated when the variable appears as the target (or a component of the target) of a variable assignment statement, (indirectly) when it is associated with an interface object of mode out or linkage, or when one of its subelements (individually or part of a slice) is updated. The value of a file is said to be updated when a WRITE operation is performed on the file object.

Permanent link update - Creation date 2021-04-03


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