Glossary VHDL / Term
A construct that defines how component instances in a given block are bound to design entities in order to describe how design entities are put together to form a complete design.
Defines the "binding" of each component instance to an entity, and each entity to an architecture. Can be defined using a configuration library unit or from within an architecture.
Permanent link configuration - Modification date 2021-09-12 - Creation date 2021-04-03